1. Field of the Invention
The invention relates generally to PCI bus communication and, more specifically, relates to use of Device ID Messaging (“DIM”) to accomplish broadcast message exchange through one or more PCI bus segments.
2. Discussion of Related Art
PCI buses have become common in computing and other electronic systems for coupling peripheral device interface components with associated processing components. Most present day personal computers as well as higher performance server systems include one or more PCI buses adapted for coupling high speed and low speed I/O devices to one another and to associated processors. Such processors may include, for example, a general purpose central processing unit (“CPU”) within the computer or a special purpose processor such as a direct memory access controller (“DMAC”).
PCI bus standards and specifications have evolved over the past years to incorporate numerous additional features and enhanced performance specifications. Published specifications for PCI buses and PCI-PCI bridge architectures, including recent versions referred to as PCI-X, are well known to those skilled in the art and are generally available at: http://www.pcisig.com/specifications. All PCI bus architecture standards available at www.pcisig.com are hereby incorporated by reference.
It is common in complex, high-performance applications to utilize multiple such PCI buses within a particular system. For example, a first PCI bus may be dedicated to interfacing with high speed peripheral devices while a second PCI bus may be reserved for interfacing with lower speed devices. Such segregation of devices onto multiple buses allows for optimizing characteristics or parameters in the operation of each bus as appropriate for the particular devices.
Where multiple buses are present in the system, is often desirable to connect all or some portion of the buses together through PCI bridge devices. A PCI bridge device couples one PCI bus segment to another PCI bus segment buffering and adapting signals as required to couple bus segments having disparate bus characteristics and timing requirements. In more complex systems several bus segments may be coupled through multiple bus bridges arranged in a hierarchical fashion. For example, some storage systems and other systems have embedded control elements that communicate amongst themselves to control operation of the system. The control elements (i.e., storage controllers, host adapters, Fibre Channel I/O adapters, etc) may communicate with one another via a hierarchical arrangement of PCI buses. Regardless of the particular hierarchy and architecture used in such complex systems, PCI bus bridges generally allow any master device on any PCI bus segment to exchange information with any slave device on any other PCI bus segment. Such flexibility may be provided while maintaining segregation of the various devices on each segment allows for controlling utilization of bus bandwidth according to performance characteristics and requirements of the various devices.
Frequently it is desirable to broadcast a message to all devices on a particular PCI bus segment. Current PCI bus standards permit such a broadcasting within a particular PCI bus segment. In other words, one device on a PCI bus segment may broadcast a message to all other devices on the same bus segment. However, in more complex systems having multiple PCI buses coupled together through one or more PCI bridge devices, such broadcasting is problematic. PCI bus bridge devices are not required by PCI specifications to forward such a broadcast message from one PCI bus segment to another. It is therefore a problem to broadcast PCI bus transactions through bus bridge's and multiple bus segments in a complex system architecture.
One present a solution to work around the inability to forward broadcast messages through PCI bus bridges has been to provide additional signal paths above and beyond those specified for the PCI bus. Such additional signal paths are often referred to as sideband signals in the sense that they are apart and distinct from standard signals defined by the PCI bus specifications. Such sideband signals may be defined as additional physical paths above and beyond those defined by PCI bus specifications or may be defined as nonstandard utilization of reserved or otherwise defined signal paths in the PCI bus standards. In the former case, additional signal paths may add significant cost and complexity to a system while the latter solution utilizes defined signal paths otherwise defined by PCI bus specifications and is therefore inconsistent with the PCI bus standards.
Another present approach to working around limitations on broadcasting PCI bus messages provides for generating multiple copies of such a message each being addressed specifically to each device known to be present on the PCI buses. These messages do not rely on bus bridge devices to forward broadcast messages but rather specifically address each of the multiple copies as a message to a specific device. Such a workaround may dramatically increase bus utilization in the system and thereby reduce overall performance of the system.
It is evident from the above discussion that improve methods and structures are needed to provide, in effect, broadcast features for PCI bus transactions but in systems utilizing multiple PCI bus segments interconnected through one or more PCI bus bridge devices.